1. Field of the Invention
The invention relates in general to a package structure having silicon through vias, and more particularly the package structure having silicon through vias filled with conductor connected to ground potential.
2. Description of the Related Art
Wire bonding chip packaging and Flip chip packaging are known chip interconnect technologies. Wire bonding chip microelectronic assembly is the electrical connection using face-up chips with a wire connection to each chip bond pad. In contrast, flip chip microelectronic assembly is the direct electrical connection of face-down (hence, “flipped”) electronic components onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip bond pads. Both processes offer advantages and disadvantages. For manufacturers, cost, performance and form factor have become the key drivers in selecting between wire bonding and flip-chip bonding as the interconnecting method of chip packaging. For example, the flip chip packaging with the die flipped over and placed face down provides the advantage of small form factor, but it is quite expansive to produce the flip chip packaging (ex: formation of conductive bumps connecting the die to a carrier). For the packaging typically with I/Os in the range of 100-600, the existing infrastructure, flexibility and materials/substrate costs of wire bonding chip packaging provide dominant advantages.
For the wire bonding chip packaging, the pads at the front side of the chips are typically grounded by bonding wires. This conventional grounding mechanism would raise issue of signal interference between the long wires, and may have considerable effect on the electrical performance of the device.